`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/03/03 17:07:09
// Design Name: 
// Module Name: bit8_bit16
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
module bit8_bit16(
input clk,
input rst,
input [7:0]bit_8,
input bit8_valid,
output reg[15:0]bit_16,
output reg bit16_valid
    );
reg bit_cnt;
always@(posedge clk or posedge rst)begin
if(rst)
bit_cnt <= 1'b0;
else if(bit8_valid)
bit_cnt <= bit_cnt + 1'b1;
end

always@(posedge clk or posedge rst)begin
if(rst)
bit_16 <= 16'b0;
else if(bit8_valid)
bit_16 <= {bit_16[7:0],bit_8};
end

always@(posedge clk or posedge rst)begin
if(rst)
bit16_valid <= 1'b0;
else if(bit8_valid && bit_cnt)
bit16_valid <= 1'b1;
else
bit16_valid <= 1'b0;
end

endmodule
